View T6C96A_3157972.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

T6C96A 2002-02-13 1 toshiba cmos digital integrated circuit silicon monolithic T6C96A overview the T6C96A is an advanced-function 4-bit single-chip microcontroller that integrates rom, work ram, i/o ports, timers and lcd driver, etc., into one chip. the T6C96A features low power consumption. features rom: 4096 words (1 words = 14 bit) work ram: 1024 bits (16 16 4 bit) subroutine nesting level: 4 levels timers: 500 ms125 ms31.25 ms ( 1ch each) in ports: 4 bit io ports: 8 bit io ports for data: 1 bit (tristate i/o) o ports: 4 bit output ports for clock: 1 bit (high-speed clock output pins) output port external device control pin: none display types: 24-segment 4 common 1/4 duty, 1/3 pre-bias minimum instruction execution time: 2.23 s (high-speed clock 3.58 mhz) 244 s (low-speed clock 32.768 khz) power-saving functions: high-speed operation mode low-speed operation mode stop mode off mode
T6C96A 2002-02-13 2 pin functions pin name i/o function circuit configuration initial in11~in14 in 4-bit input ports h io11 io i/o ports with output latch 3-state output buffer l io12 io i/o ports with output port h io13~io14 io21~io24 io31 io i/o ports with output latch l o11~o14 o output port with latch l 3-state output o21 p n p n push pull output
T6C96A 2002-02-13 3 pin name i/o function circuit configuration initial hclk o output the inverted waveform of the high-speed clock or the waveform of the high-speed clock divided in harf. l r in r out in o terminals for connecting oscillation resistor for high-speed clock oscillator /ac in system reset terminal h ts1~ts3 in used by toshiba for shipping test. fix the level of this terminal ?l?. l v dd v ss power supply 4.5 v~5.5 v 0 v (gnd) s 1 ~s 24 o segment signal output terminal ( * ) c 1 ~c 4 o common signal output terminal ( * ) total 54 pin p: p-ch tr output ability n: n-ch tr output ability ( * ) high level when display is off pad assignment x y s 13 s 12 s 11 s 10 s 9 s 8 s 7 s 6 s 5 s 4 s 3 s 2 s 1 c 1 /ac v dd r ou t r in hcl k ts1 ts2 ts3 o11 o12 o13 o14 in14 in13 in12 in11 io31 io24 io23 io22 io21 io14 io13 io12 io11 v ss s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 s 24 c 4 c 3 c 2 push-pull output
T6C96A 2002-02-13 4 block diagram io1 io2 io3 ot1 timer select acc t x row column work ram display ram y ca ad jf c in a b a/s segment buffer s 1 ~s 24 display timing generator c 1 ~c 4 instruction decoder (id) c- cnt system control signal rom pc timing generator 1 2 500 ms 125 ms 31.25 ms in11~in14 io11~io14 io21~io24 io31 o11~o14 r out r in hclk v ss v dd /ac ts1, ts2, ts3
T6C96A 2002-02-13 5 example of T6C96A ic card reader system io12 bld io22 hclk o12 io11 in11 in12 in13 in14 v ss t6c96 a key1 key2 key3 key4 tr v dd r out io21 r r in /ac sw v cc clock reset data v ss use of an external bld allows you to monitor the ic card?s supply voltage of T6C96A. io11 is 3-state type so as to use it as data line. hclk is a supply control terminal from the driver to the ic card. high-speed oscillation external resistor c 1 ~c 4 s 1 ~s 24 lcd
T6C96A 2002-02-13 6 internal cpu functions program memory (rom) instruction codes are stored in the program memory. the instruction next in line to be executed is read from the address indicated by the content of the program counter. each word in program memory consists of 14 bits, and each instruction consists of one word. figure 1 shows the program memory map. figure 1 program memory map when creating a user program, note that a specific area is occupied by the test program used by toshiba for its shipping tests. test program area test program area subroutine stating address area test program area 0000h 000fh 0010h 001fh 0020h 0bdfh 0be0h 0bffh 0c00h 0ff7h 0ff8h 0fffh
T6C96A 2002-02-13 7 test program the T6C96A requires the following test programs to be included with user programs. note that the following test program areas are not available to users. address object org 0be0h 0be0 091e oib1 14 0be1 092f oib2 15 0be2 093c oib3 12 0be3 094d otb1 13 0be4 095a otb2 10 0be5 096b otb3 11 0be6 0030 rom1 rom 0be7 0000 nop 0be8 0001 car 0be9 3bf6 jump rom2 0bea 0914 oib1 4 0beb 0925 oib2 5 0bec 0932 oib3 2 0bed 0943 otb1 3 0bee 0950 otb2 0 0bef 0961 otb3 1 0bf0 095f otb2 15 0bf1 093d oib3 13 0bf2 096e otb3 14 0bf3 091b oib1 11 0bf4 094c otb1 12 0bf5 0955 otb2 5 0bf6 0030 rom2 rom 0bf7 0000 nop 0bf8 0011 cas 0bf9 3be6 jump rom1 0bfa 092a oib2 10 0bfb 0933 oib3 3 0bfc 0964 otb3 4 0bfd 0911 oib1 1 0bfe 0942 otb1 2 0bff 0920 oib2 0
T6C96A 2002-02-13 8 address object org 0010h 0010 0000 nop 0011 0000 nop 0012 0000 nop 0013 0000 nop 0014 0000 nop 0015 0000 nop 0016 0000 nop 0017 0000 nop 0018 0000 nop 0019 0000 nop 001a 0000 nop 001b 0000 nop 001c 0000 nop 001d 0000 nop 001e 0000 nop 001f 0000 nop org 0ff8h 0ff8 0000 nop 0ff9 0000 nop 0ffa 0000 nop 0ffb 0000 nop 0ffc 0000 nop 0ffd 0000 nop 0ffe 0000 nop 0fff 0000 nop ; end
T6C96A 2002-02-13 9 program counter the program counter, which is a 12-bit binary counter (figure 2), indicates the address in program memory of the next instruction to be executed. the program counter is normally incremented each time an instruction is executed. when the count reaches 0fffh, it is reset to 000h. when the cpu is reset, the program counter and page register are both initialized to ?1?. figure 2 shows the structure of the program counter. program counter pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 figure 2 program counter table 1 is a table of change in the program counter. table 1 table of change in program counter instruction and operation condi- tion pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 jump adr jf 0 address (adr) specified in instruction calln adr 1 1 address (adr) specified in instruction executed instruction retn address stored in work ram by corresponding calln instruction address following 0fffh 0 0 0 0 0 0 0 0 0 0 0 0 reset 1 1 1 1 1 1 1 1 1 1 1 1 the program counter can directly specify addresses throughout the whole address space of the program memory. however, care is required when using the following branching instructions. (1) jump instruction [jump adr] when jump is executed, the value (adr) specified in the instruction is set in the program counter (pc11 to pc0) if the jump flag (jf) is ?0?. (2) subroutine instructions [calln adr] and [retn] when [calln adr] is executed, the value of [program counter content 1] are stored in a predetermined area of work ram as the subroutine return address, and the value (adr) specified in the instruction is set in the lower 10 bits (pc9 to pc0) of the program counter. at this point, the upper 2 bits of the program counter (pc11 and pc10) are each set to ?1?. that is, the starting address of the subroutine must be between 0c00h and 0fffh of the last page. when [retn] is executed, execution returns to the address stored using the [calln adr] instruction corresponding to n. subroutines can be nested up to 4 levels.
T6C96A 2002-02-13 10 (3) one-step branch instruction [rom] this instruction temporarily changes the output of the program counter. after [rom] instruction is executed, the instruction following by one is executed. the instruction doesn?t access the program memory directly by the contents of the program counter, but temporarily replaces the 5 th bit from the lsb of the program counter with the contents of the ca register, and the 4 bits with the contents of the accumulator with the program counter output the address following [rom] instruction. after executing one step at the branch destination, execution returns to the address of the rom instruction 2. however, if a second branching is executed from the first destination, execution is transferred to the address specified in that branch instruction. example address instruction 02e0h mvba 5 acc 5 02e1h cas ca 1 02e2h rom 02e3h nop 02e4h ***** 02e5h ***** 02e6h ***** 02e7h ***** 02e8h ***** ? 02e9h ***** ? 02eah ***** ? 02ebh ***** ? 02ech ***** ? 02edh ***** 02eeh ***** 02efh ***** 02f0h ***** 02f1h ***** 02f2h ***** 02f3h ***** 02f4h ***** instructions are executed in the order of the circled numbers. at , the accumulator is set to ?5? and, at , the ca register is set to ?1?. if [rom] is now executed, the instruction in the step after [rom] is executed and then the address in is changed into the address in replaced with the contents of ca register and accumulator, and the instruction at the address in is executed. program counter pc11~pc5 pc4 pc3 pc2 pc1 pc0 ~ ca acc execution address 02f5h ***** 02f6h ***** 02f7h ***** 02f8h ***** the instruction at is executed and execution then return to the normal address . note 1: do not use branch instructions such as [page], [jump], [call] or [ret] in position . when a branch instruction is executed at position , execution branches to the destination specified at position .
T6C96A 2002-02-13 11 x, y, and t registers x and y registers both x and y registers are 4-bit registers. they are mainly used as address registers for work ram, but can also be used as general-purpose registers. x register x8 x4 x2 x1 * specifies x address of work ram * general-purpose register t register the t register is a 4-bit general-purpose register. it can also be used to specify the x address in work ram when using the [add b] and [sub b] instructions. it can also be used to set the delay time in the [dly b] instruction. t register t8 t4 t2 t1 * general-purpose register * specifies x address of work ram * sets delay time y register y8 y4 y2 y1 * specifies y address of work ram * general-purpose register
T6C96A 2002-02-13 12 work ram the work ram is a 16 16 matrix with each cell having a 4-bit capacity. the work ram stores user data for working, lcd display data, and subroutine return addresses. lcd display data is stored in the work ram such that it corresponds to the lcd panel matrix. ?1? lights the corresponding dot, which ?0? turns it off. the position and capacity of the lcd display area is different depending on products. when making a subroutine call, the value of the address of the [calln adr] instruction 1 (program counter 1) can be stored in row x7. up to 4 values can be stored in y 0 to 3 for [call1 adr], y 4 to 7 for [call2 adr], y 8 to 11 for [call3 adr], and y 12 to 15 for [call4 adr]. when returning from a subroutine, the value stored in the work ram by the [calln adr] instruction (where n corresponds to n in [retn]) is sent to the program counter. other areas are available to the user, but because the user can also access the subroutine return address area, care must be taken not to corrupt the contents at that location. y address f e d c b a 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 c 1 9 c 2 a c 3 b c 4 c d e x address f correspond to common outputs s s 24 1 figure 3 work ram map the work ram is undefined when the power is turned on, and must therefore be initialized. subroutine return address display area
T6C96A 2002-02-13 13 a/s, accumulator (acc), carry register (ca) and jump flag (jf) a/s the a/s (adder/subtracter unit) is a circuit for calculations on 4-bit binary data. the a/s performs calculations as specified in instructions and outputs the result (4 bits) with carry data. figure 4 a/s accumulator (acc) the accumulator is a 4-bit register that stores the results of calculations. data bus a/s c in ca acc jump flag (jf) c out
T6C96A 2002-02-13 14 carry register (ca) the carry register is a 1-bit register that stores the carry data output from the a/s. it can be set to ?0? or ?1? by instructions. whichever value remains unchanged until the next instruction is executed that has an effect on the carry register setting. as shown in figure 5, the carry register can also be used in conjunction with the accumulator as a 5-bit register. a16 a8 a4 a2 a1 figure 5 ca register used in conjunction with accumulator jump flag (jf) the jump flag is a 1-bit flag consisting of the carry information output from the a/s and used as the branch condition for a jump instruction [jump]. the jump flag is set to ?1? when an instruction that sets the jump flag is executed and all conditions for the instruction are satisfied. it is kept at ?1? until the next instruction has been executed, at which point it is reset to ?0?. an unconditional jump is performed when an instruction that does not affect the jump flag is inserted before the jump instruction. note that setting the jump flag (jf) and the carry register (ca) are different processes. carry register (ca) accumulator (acc)
T6C96A 2002-02-13 15 oscillation and operating modes clock generator and timing generator the T6C96A clock generator consists of two oscillation circuits, allowing a high-speed clock (frequency fcr) and low-speed clock (frequency fxt) to be generated. by using each of these clocks in appropriate circumstances, it is possible to save power consumption. both the high-speed and the low-speed clock oscillation circuit are cr oscillation circuits. the system clock supplied to the cpu is created using the timing generator. either the high-speed or low-speed clock can be selected, using instructions, for sending to the timing generator. executing the [fcr] instruction sends the high-speed clock to the timing generator. conversely, executing [fxt] sends the low-speed clock to the timing generator. on a system reset, the high-speed clock is sent to the timing generator. either the high-speed or low-speed clock can be selected using instructions for sending to the lcd driver. executing the [dxt] instruction sends the low-speed clock to the lcd driver. clock generator the high-speed cr oscillation clock generator oscillates by the external mounting of a resistor (rosc). the high-speed cr oscillation clock generator frequency is defined as ?fcr?. the oscillation frequency of the low-speed cr clock generator is defined as ?fxt?. note the following: note 2: the value of the oscillation resistor must be selected such that fcr>fxt. note 3: due to variations in the oscillation resistor and the respective lsi characteristics, the values shown for fcr in the electrical characteristics table are only for reference. for debugging software, for example, it may be necessary to check operation with a 50% frequency variation. with reference to the above and the electrical characteristics tables, select the optimum oscillation resistance to ensure power savings. figure 6 shows the high-speed clock oscillation circuit. figure 6 high-speed clock oscillation circuit low-speed cr oscillation clock generator is built in resistor and capacitor so that external parts are not required. figure 7 shows the cr oscillation circuit for low-speed cr. figure 7 low-speed cr oscillation circuit r in r out oscillation resistor inside lsi outside lsi oscillation resistor oscillation control r in inside lsi outside lsi oscillation output oscillation control
T6C96A 2002-02-13 16 timing generator the timing generator is a circuit that generators the system clock supplied to the cpu from the source clock generated by the clock generator. the execution of instructions and cpu operations are performed in sync with the system clock. instruction executions are executed as combinations of basic instructions called ?microinstructions?. the time required to execute one microinstruction is called a machine cycle, which is one cycle of the system clock. the T6C96A instructions include 2-cycle instructions, which are executed in 2 machine cycles, 4-cycle instructions, which are executed in 4 machine cycles, 6-cycle instructions, which are executed in 6 machine cycles, and 8-cycle instructions, which are executed in 8 machine cycles. figure 8 shows the relationship between the source clock and system clock. figure 8 source clock and system clock operating modes to achieve greater power savings, the T6C96A microcontrollers have four cpu operating modes: high-speed, low-speed, stop, and off. statuses in respective operating modes high-speed operating mode in high-speed operating mode, both high-speed and low-speed clocks oscillate, the system clock being generated from the high-speed clock so that instructions are executed at high speed. the system is initialized to high-speed operating mode after a system reset. low-speed operating mode in low-speed operating mode, the high-speed clock is stopped such that only the low-speed clock oscillates, the system clock being generated from the low-speed clock so that instructions are executed at low speed. stop mode in stop mode, the high-speed clock is stopped such that only the low-speed clock oscillates. the system clock is stopped and the cpu is therefore also stopped. the internal status of the cpu is maintained. off mode in off mode, both high-speed and low-speed clocks are stopped such that both the cpu and display system are also stopped. the internal status of the cpu is maintained. table 2 shows the oscillation circuits, cpu, and lcd driver status in the respective operating modes. table 2 oscillation circuit, cpu, and lcd driver statuses in operating modes high-speed operating mode low-speed operating mode stop mode off mode high-speed clock oscillating stopped stopped stopped low-speed clock oscillating oscillating oscillating stopped cpu high-speed clock low-speed clock stopped stopped lcd display display available display available display available no display system clock source clock 1/fcr or 1/fxt (s) machine cycle
T6C96A 2002-02-13 17 transition between operating modes at power-on and at resetting the system defaults to high-speed operating mode when the power is turned on or after a system reset. transition from high-speed operating mode the [fxt] instruction transfers from high-speed to low-speed operating mode. stop mode is selected by executing the [stop] instruction. off mode is selected by executing the [off] instruction. when stop mode or off mode have been selected from high-speed operating mode, high-speed operating mode resumes when those modes are exited. after resuming operation, instructions start to be executed from the step following execution of the [stop] or [off] instruction. note 4: neither [stop] or [off] are executed when an ?l? level signal is input to the in terminal, or when the timer f/f corresponding to the content of the tim register is set. transition from low-speed operating mode the [fcr] instruction transfers from low-speed to high-speed operating mode. stop mode is selected by executing the [stop]? instruction. off mode is selected by executing the [off] instruction. when stop mode has been selected from low-speed operating mode, low-speed operating mode resumes when that mode is exited. when off mode has been selected form low-speed operation mode, high-speed operation mode resumes when that mode is exited. after resuming operation, instructions start to be executed from the step following execution of the [stop] or [off] instruction. note 5: neither [stop] or [off] are executed when an ?l? level signal is input to the in terminal, or when the timer f/f corresponding to the content of the tim register is set. resumption from stop mode there are two methods of resuming operation from stop mode, as follows: (1) resumption using in terminal when an ?l? level signal is input to one of the normally pulled up in terminals (in11 to in14) (2) resumption by timer when the timer f/f corresponding to the content of the tim register is set when stop mode has been selected from high-speed operating mode, the system resumes high-speed operation when the stop mode is exited. when stop mode has been selected from low-speed operating mode, the system resumes low-speed operation when the stop mode is exited. note 6: [stop] is not executed while the conditions for resuming operation from stop mode are satisfied. note 7: see timer description for details.
T6C96A 2002-02-13 18 resumption from off mode there is only one method of resuming operation from off mode, as follows: (1) resumption from in terminal when an ?l? level signal is input to one of the normally pulled up in terminals (in11 to in14) note that the system is initialized to high-speed operating mode on resuming operation whether off mode was selected from high-speed or low-speed operating modes. note 8: [off] is not executed when the conditions for resuming operation from off mode are satisfied or when the timer f/f corresponding to the content of the tim register is set. figure 9 shows the transition between operating modes. figure 9 operating mode status transition diagram high-speed operating mode reset [stop] stop mode low-speed operating mode [fxt] [fcr] stop mode [stop] off mode [off] [off]
T6C96A 2002-02-13 19 timer the timer is created by splitting the low-speed clock source oscillation (typ. 32.8 khz) using a 16-stage binary counter. the 10 th stage outputs a 31.25 ms signal, the 12 th stage a 125 ms signal, the 14 th stage a 500 ms signal, and the 16 th stage a 2 s signal. these four signals set specially provided timer f/fs. the timer functions are implemented by checking the statuses of these f/fs. when a cr oscillation is used for the low-speed clock, the timer signals are not output with precision timing. figure 10 shows the timer structure. figure 10 timer structure the timer has the following 3 functions: (1) detection of 31.25 ms, 125 ms and 500 ms signals by instructions (2) exiting stop mode (3) checking the oscillation status of the quartz oscillation circuit 1 reset reset [off] s r q 2 s ck r q 500 ms 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 jf ck r q 125 ms ck r q 31.25 ms timer signals [xtch] [500 ms] [125 ms] [32 ms] stop mode exit signal tim1 tim2 tim4 tim registers low-speed clock
T6C96A 2002-02-13 20 detection of 31.25 ms, 125 ms and 500 ms signals by instructions the statuses of f/fs of the 31.25 ms, 125 ms and 500 ms signals can be checked using instructions [32 ms], [125 ms] and [500 ms]. if the timer f/f is set, the jump flag is set (the ca register is not set). at the same time, the timer f/f is reset and again set at the next timing pulse. figure 11 shows the timer signals output from the 16-stage timer f/f and the respective timer f/f timing. figure 11 timing for setting timer f/fs exiting stop mode executing [tim] sends the lower 3 bits of acc to the tim register. tim1 corresponds to the 31.25 ms timer signal, tim2 to 125 ms, and tim4 to 500 ms, and check the timer f/fs. if, when checked, the timer f/f corresponding to the bit of the set tim register is set, stop mode is exited. if two or more bits are set to ?1?, the stop mode exit signal is generated at the respective timings. the timer f/f is not reset. figure 12 shows the timer signal output from the 16-stage timer f/f and the timing of the stop mode exit signal according to the content of the tim register. figure 12 stop mode exit signal 125 ms signal 31.25 ms signal timer f/f reset 500 ms signal 31.25 ms timer f/f when the [32 ms], [125 ms] or [500 ms] instruction is executed, the timer f/f is reset and the jump flag (jf) is set. 125 ms timer f/f 500 ms timer f/f 125 ms 31.25 ms reset 500 ms tim1 1 tim2 1 tim4 1 stop mode exit signal corresponding to content of tim registerv
T6C96A 2002-02-13 21 external interface the T6C96A has one 4-bit input port, input-output port, and output port (in port i/o port o port). the ports are used to ?exchange data with peripheral circuits? by executing instructions. first of all, the following is an explanation on port descriptions. in the case of iomn (n 1 to 4) being used as the description, m represents the port number and n represents the port?s internal terminal number. for example, io2 indicates the second io port, and io23 indicates the third terminal of the second io port. input ports (in ports) in ports are dedicated four terminal, four bit input ports, and the data input through the in ports is stored in the accumulator. as the in terminals are constantly subject to pull-up within the lsi, simple input circuits can be created with a minimum of external components. figure 13 shows the configuration of the in terminals. figure 13 in terminal configuration in the normal mode figure 14 shows an example of timing using the input instruction [iin] to fetch in port data into the accumulator. figure 14 in port input timing input data in terminal pull-up resistance v dd system clock source clock iin instruction input strobe a ccumulator input data
T6C96A 2002-02-13 22 the in ports also function for exiting the stop and off modes. when the mcu is in stop or off mode, inputting an ?l? level signal to one of the normally pulled-up in terminals exits the stop or off mode. figure 15 shows the structure of a circuit for creating the signals for exiting the stop and off modes. please also refer to the timer in figure 10. figure 15 stop and off mode exit signal from in port stop mode exit signal from timer in11 in12 in13 in14 stop and off mode exit signal
T6C96A 2002-02-13 23 io ports each T6C96A port consists of two four-bit io ports (io11 to io14, io21 to io24) and one single-bit io port (io31). port io11 has a 3-state structure equipped with output latching which enables hi-z when the o21 control signal (single-bit) is set with software. the o21 control signal for [otb2 1] is initialized with ?l? when reset. figure 16 shows the configuration of the io11 terminal. figure 16 io11 terminal configuration ports io12 to io14, io21 to io24 and io31 employ a method that does not utilize 3-state buffers. this method creates large ?h? level output resistance for the inverter?s p channel transistors used for the output. figure 17 shows the configuration of these terminals. figure 17 io12 to io14, io21 to io24 and io31 terminal configuration as the performance of the n-ch transistor used for output is large when the latch data in the output latch is ?l?, there will be cases where the ?h? level in acc cannot be loaded despite the [iniom] input instruction being executed. it is therefore necessary to execute the [oibm 15] instruction and set the inverter?s p channel transistor at on prior to executing the input instruction. o21 io11 1 h-imp 0 io11? io11 io11 input command io11? to cpu /o21 io output latching output data i/o switching signal v dd p-ch n-ch input data
T6C96A 2002-02-13 24 io port input timing figure 18 shows an example of the input instruction [iiom] for reading data via an io port with nothing connected to the io port. figure 18 input timing of io port system clock source clock iiom instruction i/o select signal io port input data input strobe a cc
T6C96A 2002-02-13 25 io port output timing figure 19 shows an example of using the 2-cycle io port output instruction [oiam]. this instruction outputs the content of the accumulator (acc) to port iom. figure 19 io port output timing for [oiam] instruction figure 20 shows an example of using the 4-cycle io port output instruction [oibm b]. this instruction writes immediate data b (4 bits) to the accumulator (acc) and outputs that data to port iom. figure 20 io port output timing for [oibm b] instruction figure 21 shows an example of using the 8-cycle io port output instruction [oir]. this instruction writes the content of work ram specified by the contents of the x and y registers to the accumulator (acc), then outputs the data to port io1. it then writes the contents of the work ram specified by the contents of the x and y registers 1 to the acc, then outputs that data to port io2. figure 21 io port output timing for [oir] instruction instruction system clock oiam a cc iom output data content of acc instruction system clock oibm b a cc iom b b (content of acc) instruction system clock oir a cc io1 r (x, y) r (x, y) r (x, y 1) io2 r (x, y 1)
T6C96A 2002-02-13 26 output ports (o) o ports are 4-bit output only ports with 4 terminals. all are push-pull structures with latches. when the output instruction is executed, the output data is latched before being output. the latch is initialized to the ?l? level when the mcu is reset. figure 22 shows the structure of an o terminal. figure 22 o terminal structure the following shows o port output timing. figure 23 shows an example of the 2-cycle o port output instruction [otam]. this instruction outputs the contents of the accumulator (acc) to port om. figure 23 o port output timing for [otam] instruction figure 24 shows an example of the 4-cycle o port output instruction [otbm b]. this instruction writes immediate data b (4 bits) to the accumulator (acc) and outputs that data to port om. figure 24 o port output timing for [otbm b] instruction o terminal output data output latch instruction system clock a cc om otam output data content of acc instruction system clock a cc om otb1 b b b (content of acc)
T6C96A 2002-02-13 27 hclk the hclk is mainly used for outputting a high-speed cr oscillation (3.58/1.79 mhz) clock. the hclk pin is controlled using the output instruction [iobm b] by which output data to the io11 to io14 and io31 pins are determined. either the high-speed cr oscillation frequency (3.58 mhz) or half of that frequency (1.79 mhz) output from the hclk pin can be selected as shown in the mask option table below. please request the desired mask option at sampling. table 3 mask option al code hclk output frequency al7432 high-speed cr oscillation frequency (3.58 mhz) al7434 high-speed cr oscillation frequency 1/2 (1.79 mhz) a structural diagram of the hclk circuit is shown below. io14 io13 io31 ( s1) s2 hclk 1 * 0 * 0 1 * 1 * 1 0 1 * clk * 1 clk * 1 * : don?t care * 1 : when mask option al7434 is selected, clk 1/2 is output. figure 25 hclk structural diagram binary counter r high-speed clock io13 io14 io31 * the dotted line indicates that al7432 is selected. s1 s2 out sel hclk
T6C96A 2002-02-13 28 the relation between the source clock and hclk is as follows: when mask option al7432 is selected (hclk high-speed cr oscillation frequency output is selected) when mask option al7434 is selected (hclk high-speed cr oscillation frequency 1/2 output is selected) note 9: when the high-speed cr oscillation frequency divided in half is selected (al7434 selected), to start the signal output from the hclk pin at low level, initialize the binary counter using the following procedure when starting the lsi and when stopping the hclk output. oib3 0000b ; outputs low to io31. oib1 11 ** b ; changes hclk output to s1 (io31 low) and simultaneously resets binary counter because the asterisks ( ** ) are the output values of io12 and io11, make settings accordingly. hclk source clock hclk source clock
T6C96A 2002-02-13 29 lcd driver the T6C96A microcontrollers incorporate an lcd driver for driving an lcd and the necessary control circuit. it has 96 lcd pixels (segements common). lcd driver structure figure 26 shows the structure of the lcd driver. figure 26 structure of lcd driver the lcd drive timing is derived from either the high-speed or low-speed clock. at a system reset, the system is initialized to the high-speed clock, but the low-speed clock can be selected by executing an instruction. when in low-speed operating mode, the lcd driver should also use the low-speed clock. when the lcd driver uses the low-speed clock, the lcd display can be continued even in stop mode. v 1 seg1 to lcd drive timing control circuit com1 to select high-speed oscillation clock generator low-speed oscillation clock generator work ram display data v 1 , v 3 v 2 v 2 v 3 segment driver common driver inside lsi outside lsi lcd drive power supply circuit
T6C96A 2002-02-13 30 method of lcd drive the T6C96A microcontrollers have a display area in the work ram. by writing data to this display area, a display waveform is automatically output from the segment terminals. the display area is a bitmap that corresponds one-to-one with the lcd display pixels. if an area as indicated in figure 27 is included within the work ram, a 24 4 bit map as shown in figure 29 exists owing to the fact that each cell consists of four bits, as indicated in figure 28. y address f e d c b a 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 c 1 9 c 2 a c 3 b c 4 c d e x address f correspond to common outputs s s 24 1 figure 27 map of work ram figure 28 cell structure of work ram 5 4 3 2 1 0 y/x c 1 8 c 2 9 c 3 a c 4 b s 24 s 1 figure 29 bitmap of display area subroutine return address display area one cell of work ram msb lsb a rray in a cell
T6C96A 2002-02-13 31 lcd drive power supply circuit the lcd drive power supply circuit generates the v 1 , v 2 and v 3 voltages supplied to the common and segment drivers. v 1 , v 2 and v 3 are generated by using the frame pulse to control the resistance dividing circuit between v dd and v ss . figure 30 shows the structure of the lcd drive power supply circuit. figure 30 structure of lcd drive power supply circuit note 10: r 1 :r 2 :r 3 :r 4 r 1 :r 2 :r 3 :r 4 if the ratio between r 1 , r 2 , r 3 and r 4 (the dividing resistance) is 1:1:1:1, we achieve a 1/3 prebias. to improve the through rate when switching the lcd elements on/off, a large current is caused to flow at the instant the common is switched. concretely, the large current flows only when the lcd element turns on (current in both r n and r n ), after that, the current is reduced (current only in r n ) for power saving. the T6C96A microcontrollers have a power saving function that operates by turning the display power supply on/off. when [dpon] is executed, the display power supply turns on. when [dpoff] is executed, it turns off. display power supply on/off [dpon] [dpoff] r 1 to segment driver r 2 v dd r 3 r 4 frame pulse resistance switching signal v 3 v 2 v 1 to common driver r n r n r n v ss
T6C96A 2002-02-13 32 common driver the common driver circuit creates common signals with a predetermined timing. executing [don] changes the common level to on. conversely, [doff] turns it off (same as v 2 ). figure 31 shows the common signal when the [don] and [doff] instructions are executed. signal com1 is used in this example. figure 31 common signal at execution of [don] and [doff] figure 32 shows the structure of the common driver. figure 32 structure of common driver [doff] execution [don] execution common generation pulse com2 comn com1 v dd v ss v 2 [don] [doff] latch decoder common counter frame pulse
T6C96A 2002-02-13 33 segment driver the segment driver circuit generates segment signals using the timing determined from the content of the work ram. figure 33 shows the structure of the segment driver. figure 33 structure of segment driver x address decoder seg2 segn seg1 v 3 frame pulse latch display area in work ram v 1 common counter common generation pulse
T6C96A 2002-02-13 34 using display control instructions this section explains how to use the display control instructions described in the previous pages. the instructions for selecting the clock used to generate the lcd display timing are placed at the beginning of a user program. then, after data has been written to the work ram, [dpon] is executed to turn on the display power supply, followed by [don] to set the common signal level to ?on? and effect the lcd display. figure 34 flow of operations to displaying data on lcd start if required, place [dxt] instructions at the start of the user program. (note) the system is initialized to the high-speed clock when reset. select clock for display timing. write data to display area of work ram. execute [dpon] execute [don] lcd display write the data to be displayed to the display area of work ram. turn on the display power supply. the system is initialized to the [dpon] status after a system reset. set the common signal level to ?on? (note) the system is initialized to the [doff] status after a system reset.
T6C96A 2002-02-13 35 special T6C96A instructions [add b] this instruction performs addition operations on decimal numbers. the result is also stored as a decimal. executing [add b] adds the content of work ram specified by the x and y registers and the content of work ram specified by the t and y registers to ca. the result is stored in work ram as specified by the x and y registers. this operation is repeated incrementing the y register by 1 each time until an overflow occurs at y register b. example: when the content of work ram is as shown in figure 35, executing the following instructions causes the content to change to that shown in figure 36. mvbw 2, 2 mvbt4 add 7 y address f e d c b a 9 8 7 6 5 4 3 2 1 0 0 1 2 76543210 3 4 01234567 5 6 x address 7 figure 35 content of work ram before execution of [add b] y address f e d c b a 9 8 7 6 5 4 3 2 1 0 0 1 2 77777777 3 4 01234567 5 6 x address 7 figure 36 content of work ram after execution of [add b]
T6C96A 2002-02-13 36 [sub b] this instruction performs subtraction operations on decimal numbers. the result is also stored as a decimal. executing [sub b] subtracts the content of work ram specified by the t and y registers with ca from the content of work ram specified by the x and y registers. the result is stored in work ram as specified by the x and y registers. this operation is repeated incrementing the y register by 1 each time until an overflow occurs at y register b. example: when the content of work ram is as shown in figure 37, executing the following instructions causes the content to change to that shown in figure 38. mvbw 2, 2 mvbt4 sub 7 y address f e d c b a 9 8 7 6 5 4 3 2 1 0 0 1 2 76543210 3 4 01234567 5 6 x address 7 figure 37 content of work ram before execution of [sub b] y address f e d c b a 9 8 7 6 5 4 3 2 1 0 0 1 2 75308643 3 4 01234567 5 6 x address 7 figure 38 content of work ram after execution of [sub b]
T6C96A 2002-02-13 37 [dly b] executing [dly b] generates a delay of {(16 t) 2 2} machine cycles according to the content of the t register. the content of the t register is incremented by 1 each two machine cycles. two machine cycles after an overflow occurs, immediate data b is sent to the t register and normal operation then resumes. figure 39 shows the delay that is generated and the resulting content of the t register when [dly b] is executed when the content of the t register is 9. figure 39 timing of [dly b] execution instruction system clock t register dly b mvbt 9 9h 0ah 0bh 0ch 0dh 0eh 0fh 0h b delay overflow
T6C96A 2002-02-13 38 configuration this section contains notes on mounting T6C96A microcontrollers. /ac (reset) when the power supply voltage is within the operating voltage range, keeping the level of the /ac terminal ?l? for a minimum of 100 s initializes the entire contents of the lsi. when the level of the /ac terminal changes to ?h?, the reset operation is canceled and program execution starts. the /ac terminal is internally pulled up, and it is therefore possible to create a simple reset circuit using only one switch. figure 40 shows a simple reset circuit. figure 40 example reset circuit ts (test) the ts terminal is used for the shipping test by toshiba and has a built-in pull-down resistor. for normal use, the ts terminal level should be fixed ?l? as shown in figure 41. figure 41 treatment of ts terminal inside lsi outside lsi pull-up resistor /ac v dd v ss inside lsi outside lsi pull-down resistor ts v ss
T6C96A 2002-02-13 39 r in and r out the r in and r out terminals are connected inside the lsi to the clock generators. connect a resistor between r in and r out as shown in figure 42. setup the frequency form 42.6 khz upward. figure 42 method of connecting oscillator r in r out oscillation resistor
T6C96A 2002-02-13 40 instruction tables in addition to the normal move, calculate, bit manipulation, and input-output instructions, the T6C96A also has special instructions for driving a lcd. the following shows the conventions used in the instruction tables. mnemonic machine language microinstruction acc ca jf t x y cy- cles ( * 1) ( * 2) ( * 3) ( * 4) ( * 5) ( * 1) the instruction mnemonic the operation code and operand are separated by one space. the x and y operands are 4-bit data specifying the cell in work ram. operands a and b are, unless specifically mentioned in the text, 4-bit data. (an exception is the move instruction mvba (b 5 bits).) operand n is 4-bit data in move instruction trns, or indicates a specific bit 8, 4, 2, or 1 from the msb in bit manipulation instructions. operand adr is 12 bits in the branch instruction jump, and 10 bits in the call instruction. ( * 2) the instruction in machine language a, b, x, y, and n represent immediate data. the left of the string is the msb, the right is the lsb. ( * 3) microinstruction the functions of the instruction are written as microinstructions. one line corresponds to one machine cycle. rtn indicates the end of a microinstruction. when two or more microinstructions are shown in one machine cycle, they are delimited by ?/?. ( * 4) contents of registers after instruction execution 0 for those that become ?0? 1 for those that become ?1? * for those that change according to conditions for those that do not change jf for those storing the jf in the ca register others according to * 1 and * 2 ( * 5) number of machine cycles required to execute the instruction
T6C96A 2002-02-13 41 move instructions mnemonic machine language microinstructions acc ca jf t x y cy- clesv mvat 00 0000 0101 0001 t acc rtn acc 2 mvax 00 0000 0101 0010 x acc rtn acc 2 mvay 00 0000 0101 0011 y acc rtn acc 2 mvar 00 0001 0000 0000 r (x, y) acc rtn 2 mvai x, y 00 0101 xxxx yyyy r (x, y) acc rtn 2 mvta 00 0000 0101 1001 acc t rtn t 0 2 mvtx 00 0000 0101 0110 x t rtn t 2 mvty 00 0000 0101 0111 y t rtn t 2 mvtr 00 0001 0000 0010 r (x, y) t rtn 2 mvxa 00 0000 0101 1010 acc x rtn x 0 2 mvxt 00 0000 0101 0100 t x rtn x 2 mvya 00 0000 0101 1011 acc y rtn y 0 2 mvyt 00 0000 0101 0101 t y rtn y 2 mvra 00 0001 0000 0001 acc r (x, y) /ca hold rtn r (x, y) 2 mvrt 00 0001 0000 0011 t r (x, y) rtn r (x, y) 2 mvia x, y 00 0100 xxxx yyyy acc r (x, y) rtn r (x, y) 0 2 mvba b 00 0001 010b bbbb acc b8~b1, ca b16 rtn b8~b1 b16 2 mvbah b 00 0001 1000 bbbb acc b/ca hold rtn b 2 mvbt b 00 0001 1001 bbbb t b rtn b 2 mvbx b 00 0001 1100 bbbb x b rtn b 2
T6C96A 2002-02-13 42 move instructions mnemonic function mvat moves content of acc to t register. mvax moves content of acc to x register. mvay moves content of acc to y register. mvar moves content of acc to work ram specified by contents of x and y registers. mvai x, y moves content of acc to work ram specified by instruction codes x and y. mvta moves content of t register to acc. ca is set to ?0?. mvtx moves content of t register to x register. mvty moves content of t register to y register. mvtr moves content of t register to work ram specified by x and y registers. mvxa moves content of x register to acc. ca is set to ?0?. mvxt moves content of x register to t register. mvya moves content of y register to acc. ca is set to ?0?. mvyt moves content of y register to t register. mvra moves content of work ram specified by x and y registers to acc. mvrt moves content of work ram specified by x and y registers to t register. mvia x, y moves content of work ram specified by instruction codes x and y to acc. ca is set to ?0?. mvba b moves msb of immediate data b (5 bits) to ca and 4 bits on lsb side to acc. mvbah b moves immediate data b to acc. mvbt b moves immediate data b to t register. mvbx b moves immediate data b to x register.
T6C96A 2002-02-13 43 move instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles mvby b 00 0001 1101 bbbb y b rtn b 2 mvbw a, b 00 0010 aaaa bbbb x a y b rtn a b 2 mbrx b 00 0001 0110 bbbb r (x, y) b nop x x 1 rtn * x 1 4 mbry b 00 0001 0111 bbbb r (x, y) b nop y y 1 rtn * y 1 4 trns x, n 00 0011 xxxx nnnn acc r (x, y) y y n r (x, y) acc /jf y y n 1 t t 1 jf check nop jf rtn r (x, y t) 0 15 y t 1 6t 8
T6C96A 2002-02-13 44 move instructions mnemonic function mvby b moves immediate data b to y register. mvbw a, b moves immediate data a to x register and b to y register. mbrx b stores immediate data b in work ram specified by x and y registers, then increments x register. mbry b stores immediate data b in work ram specified by x and y registers, then increments y register. trns x, n moves content of work ram specified by x and y registers to work ram specified by instruction code x and (y register-n), then increments y register. this is repeated by (t register + 1) times.
T6C96A 2002-02-13 45 operation instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles adta 00 0001 0001 0101 acc, ca t acc ca rtn t acc ca jf * 2 sbta 00 0001 0001 0111 acc, ca t acc ca rtn t acc ca jf * 2 adtr 00 0001 0000 0100 t t r (x, y) rtn * t r (x, y) 2 sbtr 00 0001 0000 0110 t t r (x, y) rtn * t r (x, y) 2 adra 00 0001 0000 0101 acc, ca r (x, y) acc ca rtn r (x, y) acc ca jf * 2 sbra 00 0001 0000 0111 acc, ca r (x, y) acc ca rtn r (x, y) acc ca jf * 2 adia x, y 00 0110 xxxx yyyy acc, ca r (x, y) acc ca rtn r (x, y) acc ca jf * 2 sbia x, y 00 0111 xxxx yyyy acc, ca r (x, y) acc ca rtn r (x, y) acc ca jf * 2 adba b 00 0000 1000 bbbb acc, ca b acc ca rtn b acc ca jf * 2 sbba b 00 0000 1001 bbbb acc, ca b acc ca rtn b acc ca jf * 2 adtb b 00 0000 1010 bbbb t t b rtn * t b 2 sbtb b 00 0000 1011 bbbb t t b rtn * t b 2 adxb b 00 0000 1100 bbbb x x b rtn * x b 2 sbxb b 00 0000 1101 bbbb x x b rtn * x b 2 adyb b 00 0000 1110 bbbb y y b rtn * y b 2 sbyb b 00 0000 1111 bbbb y y b rtn * y b 2 inc x, y 00 1110 xxxx yyyy acc, ca r (x, y) 1 r (x, y) acc r (x, y) acc ca rtn r (x, y) 1 jf * 4 dec x, y 00 1111 xxxx yyyy acc, ca r (x, y) 1 r (x, y) acc r (x, y) acc ca rtn r (x, y) 1 jf * 4
T6C96A 2002-02-13 46 operation instructions mnemonic function adta adds the content of the t register to contents of acc and ca and stores the result in acc. an overflow sets ca to ?1?. sbta subtracts the contents of acc and ca from the content of the t register and stores the result in acc. a borrow sets ca to ?1?. adtr adds the content of the t register to the content of work ram specified by the x and y registers, then stores the result in the t register. sbtr subtracts the content of work ram specified by the x and y registers from the content of the t register, then stores the result in the t register. adra adds the content of the work ram specified by the x and y registers to the contents of acc and ca, then stores the result in acc. an overflow sets ca to ?1?. sbra subtracts the contents of acc and ca from the content of the work ram specified by the x and y registers, then stores the result in acc. a borrow sets ca to ?1?. adia x, y adds the content of work ram specified by instruction codes x and y to the contents of acc and ca, then stores the result in acc. an overflow sets ca to ?1?. sbia x, y subtracts the contents of acc and ca from the content of the work ram specified by instruction codes x and y, then stores the result in acc. a borrow sets ca to ?1?. adba b adds immediate data b to the contents of acc and ca, then stores the result in acc. an overflow sets ca to ?1?. sbba b subtracts the contents of acc and ca from immediate data b, then stores the result in acc. a borrow sets ca to ?1?. adtb b adds the content of the t register to immediate data b, then stores the result in the t register. sbtb b subtracts immediate data b from the content of the t register, then stores the result in the t register. adxb b adds the content of the x register to immediate data b, then stores the result in the x register. sbxb b subtracts immediate data b from the content of the x register, then stores the result in the x register. adyb b adds the content of the y register to immediate data b, then stores the result in the y register. sbyb b subtracts immediate data b from the content of the y register, then stores the result in the y register. inc x, y increments the content of work ram specified by instruction codes x and y. an overflow sets ca to ?1?. the content of work ram after incrementing is stored in acc. dec x, y decrements the content of work ram specified by instruction codes x and y. a borrow sets ca to ?1?. the content of work ram after decrementing is stored in acc.
T6C96A 2002-02-13 47 operation instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles tinc 00 0000 0011 1000 acc r (x, y) 1 r (x, y) acc converted to decimal y y 1 acc 0/ca hold acc, ca r (x, y) acc ca r (x, y) acc/rtn same as r (x, y 1) jf * y 1 6 tdec 00 0000 0011 1001 acc r (x, y) 1 r (x, y) acc converted to decimal y y 1 acc 0/ca hold acc, ca r (x, y) acc ca r (x, y) acc/rtn same as r (x, y 1) jf * y 1 6 add b 00 1011 0000 bbbb acc r (t, y) / ca hold acc, ca r (x, y) acc ca r (x, y) acc converted to decimal nop y b y y 1/jf check nop rtn result of operation 16 b 1 * sub b 00 1011 0001 bbbb acc r (t, y) / ca hold acc, ca r (x, y) acc ca r (x, y) acc converted to decimal nop y b y y 1/jf check nop rtn result of operation 16 b 1 * cmba b 00 0001 0010 bbbb nop acc, ca b acc 0 acc rtn b acc ** 4 cmbr b 00 0001 0011 bbbb acc r (x, y) acc, ca b acc 0 acc rtn b r (x, y) * * 4 cmbt b 00 0001 1010 bbbb nop t t b t 1 rtn * t b 4 /jf jf /jf jf
T6C96A 2002-02-13 48 operation instructions mnemonic function tinc decimally increments the content of work ram specified by x and y registers. if an overflow occurs, this instruction hexadecimally increments the content of work ram specified by the x register and (y register 1). tdec decimally decrements the content of work ram specified by x and y registers. if a borrow occurs, this instruction hexadecimally decrements the content of work ram specified by the x register and (y register 1). add b adds the contents of work ram specified by x and y registers to the content of work ram specified by t and y registers, and the ca register. if an overflow occurs, the jump flag (jf) is set and stored in the ca register. the content of the y register is then incremented by 1 and the above operations repeated until the value of the y register is (16-b). work ram before execution work ram after execution c n (a n b n ) 3 2 1 0 y/x 3 2 1 0 y/x a 3 a 2 a 1 0 c 3 c 2 c 1 0 example: mvbw 0, 1 mvbt 1 add 13 repeated until (16 13 3)
y 3 b 3 b 2 b 1 1 b 3 b 2 b 1 1 sub b subtracts the content of work ram specified by t and y registers, and the ca register, from the contents of work ram specified by x and y registers. if a borrow occurs, the jump flag (jf) is set and stored in the ca register. the content of the y register is then incremented by 1 and the above operations repeated until the value of the y register is (16-b). work ram before execution work ram before execution cn (a n b n ) 3 2 1 0 y/x 3 2 1 0 y/x a 3 a 2 a 1 2 c 3 c 2 c 1 2 example: mvbw 2, 1 mvbt 3 sub 13 repeated until (16 13 3)
y 3 b 3 b 2 b 1 3 b 3 b 2 b 1 3 cmba b compares acc with immediate data b and sets the jump flag (jf) if they are not the same cmbr b compares the content of work ram specified by the x and y registers with immediate data b and sets the jump flag (jf) if they are not the same cmbt b compares t register with immediate data b and sets the jump flag (jf) if they are the same
T6C96A 2002-02-13 49 bit manipulation instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles set n, x, y 01 00nn xxxx yyyy nop acc r (x, y) or n r (x, y) acc rtn r (x, y) or n 0 4 reset n, x, y 01 01nn xxxx yyyy acc n acc {r (x, y) or n} acc r (x, y) acc rtn r (x, y) and /n 0 4 check n, x, y 01 10nn xxxx yyyy r (x, y) or n r (x, y) 1 rtn * 2 bts b 00 0001 1110 bbbb t r (x, y) nop r (x, y) b or t rtn * r (x, y) before execution 4 btr b 00 0001 1111 bbbb t r (x, y) nop r (x, y) b or t b rtn * r (x, y) before execution 4 btc b 00 0001 1011 bbbb t b nop {r (x, y) or t} r (x, y) 1 rtn * b 4 cas 00 0000 0001 0001 ca 1 rtn 1 2 car 00 0000 0000 0001 ca 0 rtn 0 2 rtrr 00 0001 0000 1000 acc r (x, y) /ca hold r (x, y) acc, ca rotate right/rtn r (x, y) before execution * 2 rtrl 00 0001 0000 1001 acc r (x, y) /ca hold r (x, y) acc, ca rotate left/rtn r (x, y) before execution * 2 rtar 00 0001 0000 1010 nop acc, ca rotate right/ rtn rotated data 2 rtal 00 0001 0000 1011 nop acc, ca rotate left/ rtn rotated data 2
T6C96A 2002-02-13 50 bit manipulation instructions mnemonic function set n, x, y sets only the bit specified in immediate data n of the work ram specified in instruction codes x and y to ?1?. reset n, x, y sets only the bit specified in immediate data n of the work ram specified in instruction codes x and y to ?0?. check n, x, y sets the jf if the bit specified in immediate data n of the work ram specified in instruction codes x and y is ?1?. the following table shows the relationship between immediate data n and the instruction codes. immediate data n 8 4 2 1 machine language nn 11 10 01 00 bts b calculates the logical sum of the content of work ram specified by the x and y registers and immediate data b. the result is stored in the work ram specified in the x and y registers. example: r (x, y) 0101 0101 b 1100 1010 result of execution 1101 1111 btr b calculates the logical product of the content of work ram specified by the x and y registers and the inverted value of immediate data b. the result is stored in the work ram specified in the x and y registers. example: r (x, y) 0101 0101 b 1100 1010 result of execution 0001 0101 btc b the jf is set when the logical sum of the content of work ram specified by the x and y registers and the inverted value of immediate data b is ?1111?. example: r (x, y) 0101 0101 b 0100 1010 result of execution 1111 0101 jf no jf cas sets the ca register to ?1? car sets the ca register to ?0? rtrr rotates the contents of work ram specified by the x and y registers and the ca register rtrl rotates the contents of work ram specified by the x and y registers and the ca register rtar rotates acc with the ca register rtal rotates acc with the ca register ca r (x, y) ca acc ca acc ca r (x, y)
T6C96A 2002-02-13 51 i/o instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles iin 00 1000 1011 0000 acc in1 rtn in1 0 2 inio1 00 1000 1011 0001 acc io1 rtn io1 0 2 inio2 00 1000 1011 0010 acc io2 rtn io2 0 2 inio3 00 1000 1011 0011 acc io3 rtn io3 0 2 oia1 00 1000 1010 0001 nop io1 acc/rtn 2 oia2 00 1000 1010 0010 nop io2 acc/rtn 2 oia3 00 1000 1010 0011 nop io3 acc/rtn 2 ota1 00 1000 1110 0000 nop ot1 acc/rtn 2 ota2 00 1000 1110 0001 nop ot2 acc/rtn 2 i/o instructions mnemonic function iin fetches data to the acc from the in port inio1 fetches data to the acc from port io1 (note) execute the output instruction [oib1 15] before the input instruction. inio2 fetches data to the acc from port io2 (note) execute the output instruction [oib2 15] before the input instruction. inio3 fetches data to the acc from port io3 (note) execute the output instruction [oib3 15] before the input instruction. oia1 outputs the content of the acc to port io1 depending on the higher 2 bits of the acc, the hclk terminal is set. oia2 outputs the content of the acc to port io2 oia3 outputs the lower 1 bit of the content of the acc to port io3 depending on the lower 1 bit of the acc, the hclk terminal is set. ota1 outputs the content of the acc to port o1. ota2 the lower 1 bit of the acc sets io11 terminal to be 3-state controlled.
T6C96A 2002-02-13 52 i/o instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles oib1 b 00 1001 0001 bbbb acc b nop io1 acc rtn b 0 4 oib2 b 00 1001 0010 bbbb acc b nop io2 acc rtn b 0 4 oib3 b 00 1001 0011 bbbb acc b nop io3 acc rtn b 0 4 otb1 b 00 1001 0100 bbbb acc b nop ot1 acc rtn b 0 4 otb2 b 00 1001 0101 bbbb acc b nop ot2 acc rtn b 0 4 oir 00 1011 1010 0000 nop nop nop acc r (x, y) y y 1 io1 acc/acc r (x, y) nop io2 acc/rtn r (x, y 1) 0 y 1 8 timer instruction mnemonic machine language microinstructions acc ca jf t x y cy- cles 500 ms 00 0000 0000 0100 500 ms timer f/f check rtn * 2 125 ms 00 0000 0000 0101 125 ms timer f/f check rtn * 2 32 ms 00 0000 0000 0110 31.25 ms timer f/f check rtn * 2 tim 00 0000 0001 0000 tim acc rtn 2
T6C96A 2002-02-13 53 i/o instructions mnemonic function oib1 b outputs immediate data b to port io1 via the acc depending on the higher 2 bits of immediate data, the hclk terminal is set. oib2 b outputs immediate data b to port io2 via the acc oib3 b outputs the lower 1 bit of immediate data b to port io3 via the acc depending on the lower 1 bit of immediate data b, the hclk terminal is set. otb1 b outputs immediate data b to port o1 via the acc otb2 b the lower 1 bit of immediate data b sets io11 terminal to be 3-state controlled. oir outputs the contents of work ram specified by the x and y registers to port io1, then increments the y register and outputs the content of work ram specified by the x and y registers to port io2. timer instruction mnemonic function 500 ms sets the jf when the 500 ms timer f/f is ?1?, then resets the timer f/f 125 ms sets the jf when the 125 ms timer f/f is ?1?, then resets the timer f/f 32 ms sets the jf when the 31.25 ms timer f/f is ?1?, then resets the timer f/f tim sends the lower 3 bits of the acc to the tim register. stop mode is exited when the timer f/f corresponding to the tim register bits is set.
T6C96A 2002-02-13 54 branch instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles rom 00 0000 0011 0000 nop pc modification acc, ca nop nop nop rtn 6 jump adr 11 adr if jf 0 pc0~pc11 adr rtn 2 call1 adr 10 00 adr nop y 0 r (7, y) 15/y y 1 r (7, y) pc 1/y y 1 r (7, y) pc 1/y y 1 r (7, y) pc 1/y 0 nop rtn 0 8 call2 adr 10 01 adr nop y 4 r (7, y) 15/y y 1 r (7, y) pc 1/y y 1 r (7, y) pc 1/y y 1 r (7, y) pc 1/y 0 nop rtn 0 8 call3 adr 10 10 adr nop y 8 r (7, y) 15/y y 1 r (7, y) pc 1/y y 1 r (7, y) pc 1/y y 1 r (7, y) pc 1/y 0 nop rtn 0 8 call4 adr 10 11 adr nop y 12 r (7, y) 15/y y 1 r (7, y) pc 1/y y 1 r (7, y) pc 1/y y 1 r (7, y) pc 1/y 0 nop rtn 0 8 ret1 00 1011 1000 0000 nop y 0 y y 1 pc r (7, y) /y y 1 pc r (7, y) /y y 1 pc r (7, y) /y 0 nop rtn 0 8
T6C96A 2002-02-13 55 branch instructions mnemonic function rom the instruction to be executed after that in the step following the [rom] instruction is at the address indicated by replacing the lower 5 bits of the address following the [rom] instruction with the contents of the ca and acc. then returns to the address at which the rom instruction was executed, plus 2. however, if a branch instruction such as [jump], [call] or [ret] is executed at the branch destination, execution is transferred to the address specified in that branch instruction. jump adr if jf was not set by the instruction executed before ?jump adr?, execution jumps to the address specified in adr. call1 adr the address of this instruction 1 is stored in work ram at line x 7, y 0 to 3, and execution branches to the address specified in the instruction code (lower 10 bits of address adr, all others are ?1?). call2 adr the address of this instruction 1 is stored in work ram at line x 7, y 4 to 7, and execution branches to the address specified in the instruction code (lower 10 bits of address adr, all others are ?1?). call3 adr the address of this instruction 1 is stored in work ram at line x 7, y 8 to 11, and execution branches to the address specified in the instruction code (lower 10 bits of address adr, all others are ?1?). call4 adr the address of this instruction 1 is stored in work ram at line x 7, y 12 to 15, and execution branches to the address specified in the instruction code (lower 10 bits of address adr, all others are ?1?). ret1 returns to address stored in work ram by ?call1?
T6C96A 2002-02-13 56 branch instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles ret2 00 1011 1000 0001 nop y 4 pc r (7, y) /y y 1 pc r (7, y) /y y 1 pc r (7, y) /y 0 nop rtn 0 8 ret3 00 1011 1000 0010 nop y 8 y y 1 pc r (7, y) /y y 1 pc r (7, y) /y y 1 pc r (7, y) /y 0 nop rtn 0 8 ret4 00 1011 1000 0011 nop y 12 pc r (7, y) /y y 1 pc r (7, y) /y y 1 pc r (7, y) /y 0 nop rtn 0 8 operating mode instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles fcr 00 0000 0000 1001 system clock high-speed clock rtn 2 fxt 00 0000 0000 1000 system clock low-speed clock rtn 2 stop 00 0000 0011 0011 nop nop stop nop nop rtn 6 off 00 0000 0011 0001 nop nop off nop nop ret 6
T6C96A 2002-02-13 57 branch instructions mnemonic function ret2 returns to address stored in work ram by ?call2?. ret3 returns to address stored in work ram by ?call3?. ret4 returns to address stored in work ram by ?call4?. operating mode instructions mnemonic function fcr generates the system clock from the high-speed clock. the cpu operates at high speed. fxt generates the system clock from the low-speed clock. the cpu operates at low speed. stop transfers to stop mode off transfers to off mode
T6C96A 2002-02-13 58 display control instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles don 00 0000 0000 1011 display on rtn 2 doff 00 0000 0000 1010 display off rtn 2 dpon 00 0000 0001 1011 display power supply on rtn 2 dpoff 00 0000 0001 1010 display power supply off rtn 2 dxt 00 0000 0001 1000 display timing low-speed clock rtn 2 miscellaneous instructions mnemonic machine language microinstructions acc ca jf t x y cy- cles dly b 00 0000 0111 bbbb t t 1 jf check t b rtn b * nop 00 0000 0000 0000 nop rtn 2 /jf jf
T6C96A 2002-02-13 59 display control instructions mnemonic function don sets the common pulse level to on doff sets the common pulse level to off. common pulse v 2 dpon turns on the display power supply and generates v 1 , v 2 , and v 3 dpoff turns off the display power supply and stops generating v 1 , v 2 , and v 3 dxt generates the lcd drive timing from the low-speed clock miscellaneous instructions mnemonic function dly b makes a delay of {(16 t) 2 2} machine cycles nop no operation
T6C96A 2002-02-13 60 T6C96A electrical characteristics tables absolute maximum ratings (v ss 0 v) item symbol rating unit power supply voltage v dd 0.3~6.0 v input voltage v in 0.3~v dd 0.3 v operating temperature t opr 0~40 c storage temperature t stg 55~125 c recommended operating conditions (v ss 0 v, ta 25c) item symbol applicable terminal test circuit conditions min typ. max unit power supply voltage v dd v dd f cr 3.58 mhz 4.5 5.0 5.5 v ?h? input voltage v ih /ac, in, io v dd 0.75 v dd v ?l? input voltage v il /ac, in, io 0 v dd 0.25 v high-speed clock cr oscillation frequency f cr r in , r out v dd 5.0 v r 9.1 k 3.22 3.58 3.93 mhz low-speed clock cr oscillation frequency (low-speed cr) f crl v dd 5.0 v built in cr 24.6 32.8 42.6 khz frame frequency f r f crl 32.8 khz 48 64 83.2 hz dc characteristics (current consumption) (v ss 0 v, ta 25c) mcu block item symbol applicable terminal test circuit conditions min typ. max unit current consumption high-speed operating mode i dd (oph) v dd 5.0 v f cr 3.58 mhz 800 1600 a current consumption low-speed operating mode i dd (opl) v dd 5.0 v f crl 32.8 khz (typ.) built in cr 33 66 a current consumption stop mode i dd (stop) v dd 5.0 v f crl 32.8 khz (typ.) built in cr 30 60 a current consumption off mode i dd (off) v dd 5.0 v 0.01 3 a note 11: the overall consumption of the device is the current consumed by the mcu plus that consumed by the lcd driver.
T6C96A 2002-02-13 61 dc characteristics (current consumption) (v ss 0 v, ta 25c) lcd driver block item symbol applicable terminal test circuit conditions min typ. max unit current consumption display power supply on ilcd (on) v dd 5.0 v 14 26 a current consumption display power supply off ilcd (off) v dd 5.0 v 0.01 3 a dc characteristics (terminal ability) (v ss 0 v, v dd 5.0 v, ta 25c) item symbol applicable terminal test circuit conditions min typ. max unit ?h? output voltage v oh o11, o12, o13, o14, io11, io12, io13, io14, hclk v dd 0.2 v dd v ?l? output voltage v ol o11, o12, o13, o14, io11, io12, io13, io14, hclk 0 0.2 v hclk 2 ma ?h? output current i oh io11, o11, o12, o13, o14 v dd 5.0 v v oh 4.5 v 800 a hclk 2 ma ?l? output current i ol io11, o11, o12, o13, o14 v dd 5.0 v v ol 0.5 v 800 a ?h? output current i oh io12, io13, io14, io21, io22, io23, io24, io31 v dd 5.0 v v oh 4.5 v 11 a ?l? output current i ol io12, io13, io14, io21, io22, io23, io24, io31 v dd 5.0 v v ol 0.5 v 800 a pull-up resistance rpu /ac, in, in11, in12, in13, in14 v dd 5.0 v 42 60 78 k input leakage current i ih i il io11 v dd 5.0 v v in 0 v or 5.0 v 1 1 a
T6C96A 2002-02-13 62 dc characteristics (terminal ability) (v ss 0 v, ta 25c) lcd driver block item symbol applicable terminal test circuit conditions min typ. max unit ?h? output voltage v oh seg, com v dd 0.2 v dd v ?l? output voltage v ol seg, com 0 0.2 v ?h? output current i oh seg, com v dd 5.0 v v oh v dd 0.5 v 300 a ?l? output current i ol seg, com v dd 5.0 v v ol v ss 0.5 v 300 a
T6C96A 2002-02-13 63 addendum pad coordinates chip size : 2.82 2.82 (mm) chip thickness : 450 ( m) pad size : 100 100 ( m) number of pads : 54 substrate voltage : v ss (unit: m) pad name x point y point pad name x point y point c 1 901 1167 s 1 901 1167 /ac 751 1167 s 2 751 1167 v dd 600 1167 s 3 600 1167 r out 450 1167 s 4 450 1167 r in 300 1167 s 5 300 1167 hclk 150 1167 s 6 150 1167 ts1 32 1167 s 7 0 1167 ts2 182 1167 s 8 150 1167 ts3 333 1167 s 9 300 1167 o11 483 1167 s 10 450 1167 o12 633 1167 s 11 600 1167 o13 783 1167 s 12 751 1167 o14 933 1167 s 13 901 1167 v ss 1163 975 s 14 1163 976 io11 1163 825 s 15 1163 826 io12 1163 675 s 16 1163 676 io13 1163 525 s 17 1163 526 io14 1163 375 s 18 1163 375 io21 1163 225 s 19 1163 225 io22 1163 75 s 20 1163 75 io23 1163 75 s 21 1163 75 io24 1163 225 s 22 1163 225 io31 1163 375 s 23 1163 375 in11 1163 526 s 24 1163 525 in12 1163 676 c 4 1163 675 in13 1163 826 c 3 1163 825 in14 1163 976 c 2 1163 975
T6C96A 2002-02-13 64 toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. the products described in this document are subject to the foreign exchange and foreign trade laws. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. the information contained herein is subject to change without notice. 000707eb a restrictions on product use

▲Up To Search▲

Price & Availability of T6C96A

	To Download T6C96A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .